LiDAR (light detection and ranging) is a core technology for three-dimensional spatial perception and high-precision distance measurement, playing an irreplaceable role in many key fields such as autonomous driving and remote sensing mapping. With the continuous expansion of application scenarios, the requirements for LiDAR systems for resolution, detection distance, and dynamic adaptability are increasingly heightened. This poses greater challenges for the readout circuit, which serves as the core of signal acquisition and processing. The readout circuit must meet strict requirements for high-speed data conversion, low-noise suppression, and wide-range clock compatibility to ensure the accuracy, stability, and real-time performance of signals. Currently, most research in academia and industry focuses on the performance optimization of individual analog functional modules within the readout circuit, while insufficient attention is paid to the overall architectural innovation of the logic timing control system. This often causes traditional readout circuits to encounter key technical bottlenecks during high-speed parallel data processing, such as excessive synchronization errors, noise coupling induced by external interference, and insufficient stability of cross-clock domain data transmission, which severely restricts the overall performance improvement of LiDAR systems.
A novel on-chip logic controller for LiDAR readout circuits was constructed through systematic architectural design and algorithm development. The overall architecture of the logic controller comprised four core units: the row gating module, the column gating module, the parallel-to-serial conversion module, and the control signal generation module. These modules worked in coordination to achieve accurate sampling, quantization, and readout of pixel array data. In the specific design, a “4-bit synchronous counter + shift register” architecture was adopted to optimize the timing matching problem in high-speed parallel-to-serial conversion. A semi-autonomous row-column gating circuit was designed based on cascaded D flip-flops to reduce noise interference introduced by external control signals. A dynamic timing ratio algorithm was proposed, establishing a core timing ratio relationship of “1:247:896” to optimize cross-clock domain synchronization performance. To meet the level conversion requirements of the row gating module, the performance differences between a current mirror level shift circuit and a cross-coupled level shift circuit were compared and analyzed. Ultimately, the cross-coupled level shift circuit, characterized by low static power consumption and fast switching speed, was selected to achieve stable conversion of 1.8 V digital signals to 3.3 V analog signals (Fig.5). The parallel-to-serial conversion module employed a technologically mature and highly stable serial register structure, combined with a control signal generation circuit based on a synchronous counter, to accomplish efficient conversion of 12-bit parallel data to high-speed serial data (Fig.7, Fig.8). System-level timing simulation, core module simulation, and post-simulation verification were completed using software.
The simulation results demonstrated that the designed logic controller exhibited excellent comprehensive performance. At a clock frequency of 128 MHz, it successfully achieved 12-bit parallel-to-serial conversion with a synchronization error of less than 0.2 ns, effectively mitigating timing mismatch issues in high-frequency scenarios (Fig.9). The semi-autonomous row-column gating circuit based on cascaded D flip-flops reduced the maximum amplitude of glitch interference to 102 mV, approximately 50% lower than that of traditional counting-decoding gating circuits, significantly reducing the impact of noise coupling on surrounding analog circuits (Fig.11b). The dynamic timing ratio algorithm supported stable operation over a wide clock range from 32 MHz to 128 MHz, with no timing conflicts at different clock frequencies, enabling flexible adaptation to both low-speed, low-power and high-speed, high-precision detection scenarios (Fig.3, Fig.12a ~ Fig.12d). Joint simulation of the row gating circuit and the cross-coupled level shift circuit showed that the row gating signal could accurately select pixel units row by row, and the level shift circuit had a response time of only 0.15 ns, demonstrating strong switching capability and stable output (Fig.6). The collaborative operation of the control signal generation circuit and the column gating module ensured precise synchronization between the parallel-to-serial conversion control signals and the column gating clock signals, achieving efficient parallel processing of 128-column data (Fig.12e ~ Fig.12f). Post-simulation verification further confirmed that the system experienced no data loss during high-frequency operation at 128 MHz, and its overall stability and reliability were significantly enhanced.
This study, through architectural innovation and algorithm optimization, explores solutions to key technical bottlenecks such as timing mismatch, noise interference, and cross-clock domain compatibility faced by traditional logic controllers for LiDAR readout circuits. The designed “4-bit synchronous counter + shift register” architecture, semi-autonomous row-column gating circuit, and dynamic timing ratio algorithm provide a high-performance and highly reliable logic control solution for LiDAR readout circuits. This logic controller not only meets the core requirements of high-speed data conversion, low-noise suppression, and wide clock domain adaptation for high-precision LiDAR but also possesses advantages such as a simple structure and controllable power consumption. It lays an important foundation for the overall performance improvement of LiDAR systems and offers broad application prospects. Future research will further optimize the response speed of the dynamic timing algorithm and explore circuit stability designs for higher-frequency scenarios.
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