Abstract: To reduce the circuit's power and size of frequency domain equalization (FDE) system, and meet the requirements of FDE in long-distance few-mode fiber communication, the circuit for fast Fourier transformation (FFT), the key of FDE, was studied. The long point FFT operation was converted to short FFT by means of 2-D decomposition algorithm, and the hardware complexity was reduced. High-speed butterfly core based on field-programmable gate array(FPGA) was designed to implement 2-D R22SDF structure of 16384 point FFT, improve the resource utilization of memory and reduce the usage of complex multipliers. Through theoretical analysis and experiments, resource consumption information of the circuit under different clock frequencies was collected. The result show that the designed FFT can satisfy the optimization requirement of FDE circuit structure in few-mode fiber communication and realize real-time processing of 200MHz data speed in FDE.