Silicon photomultipliers (SiPMs) have become the core single-photon sensors in fields such as positron emission tomography, high-energy physics calorimeters, satellite laser ranging, and low-light light detection and ranging (LiDAR) systems. Its inherent high gain, picosecond-level response, and wide dynamic range can be fully utilized only when matched with front-end amplifiers featuring extremely low equivalent noise (sub-millivolt level), multi-hundred-megahertz bandwidth, and sub-nanosecond timing precision, while also meeting the requirements of high-density, low-power dedicated readout chips. Therefore, continuous optimization of front-end amplification architecture is crucial for improving detector sensitivity, imaging resolution, and power efficiency.

Over the past decade, research has mainly focused on two amplification concepts: voltage-mode and current-mode. The voltage-mode approach first converts the SiPM current pulse into voltage across a small resistor less than 50 Ω and then amplifies the voltage. A typical implementation is the charge-sensitive amplifier (CSA), which uses feedback capacitor to integrate charge, with output amplitude proportional to the deposited energy (Fig.1). The most advanced CSA using 65 nm complementary metal-oxide simecondutor (CMOS) can reduce the equivalent noise charge (ENC) to 37 e^－root mean square (RMS) (Table 1), but the required feedback capacitor area is large, and the integration process limits the rise time, affecting timing precision. To break through bandwidth bottleneck, the position-energy-timing application specific integrated circuit (ASIC) (PETA) chip adopts a five-stage low-gain high-speed differential link (Fig.2) with bandwidth up to 900 MHz. The fiber tracker readout ASIC (BETA) chip uses folded cascode rail-to-rail amplifier (Fig.3), sacrificing bandwidth to 9.6 MHz but achieving extremely low power consumption of only 1.5 µW per channel (Table 1). These examples indicate that voltage-mode circuits often sacrifice bandwidth or area for low noise and low power consumption.

Current-mode architectures maintain low impedance at the input node, directly mirroring the SiPM current into parallel “fast” and “slow” branches (Fig.4). The fast branch preserves the steep rising edge for timing, while the slow branch integrates the signal for energy measurement. The simplest current buffer is common-gate transimpedance amplifier (CGTIA), with an input impedance of 1/g_M (Fig.5). programmable integrated self-test (PIST) chip implemented in 55 nm CMOS (Fig.6) achieves a bandwidth of 1.6 GHz and 200 mV/pC gain. To further reduce the input impedance without proportionally increasing power consumption, the regulated common-gate transimpedance amplifier (RCGTIA) adds local feedback, reducing input resistance by (1+A) times (Fig.7). Experiments show that the negative feedback common-gate structure increases bandwidth from 350 MHz to 500 MHz while maintaining power consumption at 3 mW (Fig.8). Lower-power ultra-low jitter compact ASIC for silicon photomultiplier (LUCAS) chip embeds flipped voltage follower (FVF) loop in the RCGTIA (Fig.9), achieving an input impedance below 10 Ω without increasing static current. Programmable multi-branch current mirror (Fig.10) distributes signals to multiple gain-weighted paths, reducing integral nonlinearity from 5.8% to 1.3% over 200 pC range. Advanced dual-loop chips such as high resolution flexible time-over threshold (HRFlexToT) (Fig.12) combine temperature-compensated feedback, achieving >500 MHz bandwidth, 35 nV/√Hz input noise, and 3.5 mW power consumption (Table 2 and Table 3).

Voltage-mode front-ends remain irreplaceable in ultra-low noise, low-count-rate scenarios (e.g., Cherenkov telescopes or spaceborne photon counters), with power consumption controllable below 100 µW and relaxed timing requirements. Current-mode circuits have become the mainstream in high-bandwidth, high-resolution systems (such as time-of-flight position emission tomography) due to low input impedance, natural matching with large SiPM capacitance, and good signal edge preservation. Future research will focus on maintaining multi-loop feedback stability under process, voltage, temperature (PVT) variations, and advancing toward 28 nm or 22 nm processes to further improve bandwidth while keeping the power consumption per channel below 5 mW.