[1] HUANG P,LUO F G, CAO M C,et al.Design of PCs cluster system of broadband optical bus interconnection network[J]. Laser Technology, 2003,27(3):264-267(in Chinese).
[2] JOSHI A,CHRISTOPHER B,KWON Y J.Silicon-photonic clos networks for global on-chip communication[C]//Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip.San Diego, CA, USA: IEEE Computer Society,2009:124-133.
[3] PAN Y, KUMAR P, KIM J. Firefly: illuminating future network-on-chip with nanophotonics[J].ACM Sigarch Computer Architecture News,2009,37(3): 429-440.
[4] VANTREASE D, SCHREIBER R,MONCHIERO M, et al. Corona: system implications of emerging nanophotonic technology[J].Proceedings of IEEE,2008,36(3):153-164.
[5] PSOTA J, MILLER J,KURIAN G,et al.ATAC:improving performance and programmability with on-chip optical networks[C]//Proceedings of 2010 IEEE International Symposium. Paris,France:Circuits and Systems(ISCAS), 2010:3325-3328.
[6] CHAN J, HENDRY G,BERGMAN K,et al. Physical-layer modeling and system-level design of chip-scale photonic interconnection networks[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2011,30(10):1507-1520.
[7] SHERWOOD-DROZ N, WANG H, CHEN L,et al.Optical 4×4 hitless silicon router for optical networks-on-chip (NoC)[J]. Optics Express,2008,16(20):15915-15922.
[8] YANG M, GREEN W M J, ASSEFA S, et al.Non-blocking 4×4 electro-optic silicon switch for on-chip photonic networks[J]. Optics Express, 2011,19(1):47-54.
[9] JI R Q, YANG L, ZHANG L, et al.Microring-resonator-based four-port optical router for photonic networks-on-chip[J]. Optics Express, 2011,19(20):18945-18955.
[10] GU H X, MO K H, XU J.A low-power low-cost optical router for optical networks-on-chip in multiprocessor systems-on-chip[C]//2009 IEEE Computer Society Annual Symposium.Tampa, FL,USA: Proceedings of VLSI, 2009: 19-24.
[11] CHAN J, HENDRY G, BIBERMAN A, et al. PhoenixSim: A simulator for physical-layer analysis of chip-scalephotonic interconnection networks[C]//Proceedings of the Conference on Design, Automation and Test. Dresden,Germany:DATE,2010:691-696.
[12] DALLYW J, TOWLES B. principles and practices of interconnection networks[M]. San Francisco, USA:Morgan Kaufmann Publishers, 2004: 89-100.
[13] CHAN J, HENDRY G,BIBERMAN A,et al.Architectural design exploration of chip-scale photonic interconnection networks through physical-layer analysis[J].Optical Fiber Communication(OFC),2010,28(9): 1305-1315.
[14] CHAN J, BIBERMAN A, LEEB G, et al. Insertion loss analysis in a photonic interconnection network for on-chip and off-chip communications[C]//Proceeding of Annual Meeting IEEE Lasers Electro-Optics Society(LEOS).Acapulco, Mexico: IEEE Lasers and Electro-Optics Society, 2008:300-301.
[15] TATSUHIKO F, TOMOHISA H, FUMIAKI O, et al.Low loss intersection of Si photonic wire waveguides[J]. Japanese Journal of Applied Physics, 2004,43(2):646-647.
[16] XIA F, SEKARIC L, VLASOV Y. Ultracompact optical buffers ona silicon chip[J]. Nature Photonics, 2007,1(1):65-71.
[17] LEEB G, ALEKSANDR B, DONG P,et al. All-optical comb switch for multiwave-length message routing in silicon photonic networks[J]. IEEE Photonics Technology Letters, 2008,20(10):767-769.
[18] GILBERT H, SHOAIB K, ALEKSANDR B, et al. Analysis of photonic networks for a chip multiprocessor using scientific applications[C]//Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip. San Diego, CA,USA:IEEE Computer Society,2009:104-113.